Larger wafers boosting GaAs and InP electronics

The boom in the compound semiconductor industry was evident at both the GaAs MANTECH conference in Washington DC and the Indium Phosphide and Related Materials conference in Williamsburg, Virginia in May, with delegate and exhibitor numbers up by as much as 50% on last year. A key concern at both was supply of larger-diameter wafers — 6″ GaAs and 4″ InP — to meet demand for electronic devices.

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• SOURCE:SCIENCEDIRECT
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• If you need more information about GaAs wafer, please visit our website: http://www.powerwaywafer.com or send us email to  powerwaymaterial@gmail.com.

Characterization of semi-polar GaN on GaAs substrates

Cubic GaN was grown on GaAs(0 0 1). The GaN layers were found to exhibit residual strain with a measured a-lattice parameter of 4.4990 Å. The GaN layers were grown on GaAs(1 1 0) forming cubic crystal structure with an a-lattice parameter of 4.4947 Å for the LT-GaN buffer layers and a hexagonal structure with an a-lattice parameter of 2.7463 Å and a c-lattice parameter of 5.5882 Å for the main GaN layers. Comparisons between the two GaAs substrate orientations, GaN on GaAs(1 1 0) showed a smoother surface (R  _rms of 5.369 nm) than that on GaAs(0 0 1) (R  _rms of 9.776 nm). It was shown by a TEM investigation that semi-polar GaN layers with low defect densities could be grown by MOCVD on GaAs(1 1 0) substrates. The TEM results indicated GaN$\mathrm{}\mathrm{}\stackrel{}{\mathrm{}}\mathrm{}$//GaAs[1 1 0] and GaN$\mathrm{}\mathrm{}\stackrel{}{\mathrm{}}\mathrm{}$//GaAs(1 1 0) crystal orientations.

Keywords

gaas wafer suppliers，gaas substrate supplier，gaas wafers,GaAs single-crystal substrates
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• SOURCE:SCIENCEDIRECT
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• If you need more information about GaAs wafer, please visit our website: http://www.powerwaywafer.com or send us email to  powerwaymaterial@gmail.com.

Atomistic structure of stacking faults in a commercial GaAs:Si wafer revealed by cross-sectional scanning tunneling microscopy

A Frank-type stacking fault bounded by a partial dislocation, about a few nanometers in size, was observed in a commercial GaAs:Si wafer (with the Si concentration of ${\mathrm{}}^{\mathrm{}}{}^{\mathrm{}}$) annealed at the temperature of about 950 K, by cross-sectional scanning tunneling microscopy. There existed no charge around the stacking fault, unlike in heavily Si-doped GaAs. There was a localized energy level associated with the stacking fault, as expected theoretically in the pure stacking fault in which Si atoms do not exist.

Keywords

• Stacking faults; 
• Si-doped GaAs; 
• Cross-sectional scanning tunneling microscopy
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• SOURCE:SCIENCEDIRECT
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GaAs side-by-side direct wafer bonding and formation of lateral pn junction

We demonstrate the first successful side-by-side lateral wafer bonding of GaAs which is expected to increase the flexibility of the device fabrication process. First we give a brief review of compound semiconductor surface-to-surface direct wafer bonding, which has been remarkably successful in device applications owing to a new dimension in the fabrication process flexibility. Then results of side-by-side direct wafer bonding, which was achieved using a pair of cleaved facets taking advantage of their quasi-perfect flat surfaces, are presented. It is shown that submicron-order leveling can be easily achieved by face-down alignment of the two wafers. Lateral nn and pn junctions have been successfully formed using bulk substrates and even with epitaxial wafers. Current-voltage characteristics across the bonded interface show that no observable electrical barrier is formed by the bonding process. Although some oxides were found to exist at the bonded interface, TEM measurements revealed that atomic-order recrystallization is achieved in most of the interface after heat treatment at 700°C for 30 min.

Keywords

• Direct wafer bonding; 
• GaAs; 
• Cleaved facet; 
• Electrical property; 
• TEM; 
• EDX
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• Source:Sciencedirect

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Graphics script provides quick classification of CaAs wafers

Infrared transmission topography has long been used to detect variations in gallium arsenide wafers that can cause dark-line defects that limit lifetime of GaAs lasers and solar cells. In the past, infrared transmission was measured over a whole wafer by scanning a small spot mechanically. Absorption was calculated at each location across the surface of the wafer and used to produce colour-coded plots that allow the wafer’s characteristics to be determined at a glance. The program ran on VAXNMS computers, but these are being taken out of service due to obsolescence. To overcome these problems, the author developed a graphics script using a state-of-the-art data analysis program which provides quick classification of CaAs wafers based on traps and defects, but runs on inexpensive personal computers and, as a bonus, produces bit-map plots that can be cut  and pasted into Windows word processing and presentation software.

Polished wafers of semiinsulating undoped GaAs or doped conducting GaAs are important for the manufacture of semiconductor devices and integrated circuits that operate at very high frequencies. Semi-insulating GaAs wafers are typically used as substrates for electronic devices, while silicon-doped wafers are used in the fabrication of solar cells and edge-emitting lasers. The advantage of GaAs is that it is capable of operating at 5 to 10 times the maximum frequency level of silicon circuits.These devices are currently used in three major consumer markets: wireless (including PCS and cellular), fibre-optic communications, and television (including cable and direct-broadcast satellite TV). There are also many military communications applications for GaAs.Unfortunately, the EL2 trap is an electronic defect in the GaAs crystal that is not yet fully understood in terms of its atomic structure. It is, however, instrumental in producing semi-insulating GaAs crystals by pinning the Fermi level near mid-gap. Uneven distributions of EL2 can cause problems in GaAs by affecting the resistivity and  device isolation. Another type of defect, crystalline dislocations, can be mapped by etching the wafer (for semi-insulating GaAs) or nondestructively (for GaAs:Si). The effects of dislocations on electronic devices fabricated on active layers grown on semi-insulating GaAs are unclear, but dislocations are unlikely to improve device characteristics. Dislocations in GaAs:Si are known to cause dark-line defects in lasers and solar cells, leading to premature failure. 

Wafer scanning

The Air Force Research Laboratory has developed an automated method of accurately measuring the infrared transmission and therefore the absorption (or scattering) at all locations across a GaAs wafer. From this, the EL2 density (or dislocation density) can be calculated. T3he wafer is mechanically scanned past a beam from a tungsten-halogen light source. The collimated  light is focused through a monochromator that passes only 1.1 l_trn wavelength light, which is absorbed b) the EL2 trap. Measurement at 1.1 urn wavelength gives neutral EL2 density, while using 1.2 nm wavelength  gives total  EL2  density  Dislocation  density  is measured  at  a  wavelength  where  the  EL2  trap  does  not  absorb;  we use  1.45  urn  wavelength  (see Figures  l-4).  Measurement  at other  wavelengths  is  required  for  other sample wafer compositions.  For example, total  iron  density  in  indium phosphide  wafers  requires  measurement  at  1.0  urn wavelength,  as shown  in Figure 5. The  light  passes  through  an electromechanical chopper  and  is  focused  into a 0.5  mm2 spot  on the wafer. A germanium diode detector operating  in the  low-noise  zero-bias mode  detects  the  infrared  light passing through  the  samp1e.A com- mercial lock-in amplifier detects  the light, digitises  its  intensity, and  the acquisition  computer  program stores  the  intensity  in  a  file  along with on-wafer coordinates. Measurement  of  the  16,597  locations  required  to  map  a  3”  wafer  takes about  an  hour;  100  mm  wafers (measured  at 28,593  locations)  and 150  mm  wafers  (measured  at 68,444  locations)  take longer. Comprehending  the  meaning  of these  large data-sets can be very difficult.  Our  analysis  constructs  a colour  histogram by ranking the  da- ta  into  14  bins  and  assigning  a colour  to  each  bin, then  plotting  a square  of  that  colour  at  each  location where  the measured value corresponds  to  a  bin  range.  This provides  an  easily  interpreted colour-map  of the  measured  values keyed to the  colour  histogram. This  provides  an  excellent method  of  investigating  relatively obscure  correlations  between  mate- rials properties  and  device  properties.The  plotted  colour-map  of  the dataset  can  easily  be  compared  to the  properties  of  semiconductor device  test  structures  fabricated  on the  wafers.  Such  measurements  as Hall-effect  for  free  carrier  density and  mobility,  sourcedrain  resistance,  source-drain  saturation  cur- rent,  pinch-off  voltage  and microwave  characteristics  such  as cut-off  frequency  can  also  be plotted as wafer-maps. Visual inspectionof the colour-maps quickly
reveals any rough correlations; more detailed mathematical correlations can be carried out as desired.

New program replaces old

Commercial data plotting packages do not use this scheme of a colour histogram with the colours keyed to locations ofmeasurements on a semiconductorwafer.A decade ago, the author began
using a custom program developed by co-workers D.Elsaesser, S. Dudley and J. Sewell, who implemented the scheme in a FORTRAN wafer-mapping program on a Digital Equipment Corp VAX/VMS super-minicomputer. Unfortunately, their


Refining plots

The user can then easily refine the plots. LabTalk usually draws too many numbers on each axis. The author corrects this by clicking the “Format” tab to get the drop-down menu, choosing “axis” and “X” (or
“Y”) and entering lower values for the number of tic marks.The axes may also be labelled by clicking on “X axis label” (or “Y axis label”) and entering new axis-label text. Origin has a layout screen that
may be used to combine the histogram and wafer-map plots on a single page for printing or plots may be saved and combined on any word processor or graphics program that supports colour.

Keywords : gaas wafer,gaas wafer price,gaas wafer cleaning,gaas wafer size,gaas wafer fabirication process,gaas wafer market

Source:Sciencedirect


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Large-depth defect profiling in GaAs wafers after saw cutting

Positron lifetime measurements and Doppler-broadening spectroscopy using slow positrons were combined to investigate open-volume defects created by sawing wafers from GaAs ingots introduced by a diamond saw cutter. The depth distribution represents a large-depth (up to 9.5 μm), wedge-like profile. This was found during step-by-step etching and assembling the respective individual S(E) curves. The depth and the concentration of the defects introduced by the diamond saw depend on the advance of the saw blade. The thermal stability of the detected defects was studied by an isochronal annealing experiment. It was concluded from the positron lifetime measurements and from the Doppler-broadening parameters as well as from the annealing behavior that small vacancy aggregates consisting of at least two vacancies are created by the sawing procedure. More extended defects such as microcracks were analyzed by scanning electron microscopy (SEM). Rutherford-backscattering spectroscopy shows that there is no amorphous material in the near-surface region.

Keywords：GaAs wafers; Saw cutting; Positron;DB; GD; PM


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Photoelastic characterization of residual strain in GaAs wafers annealed in holders of different geometry

The spatial distribution of residual strain in undoped 2 inch GaAs wafers multi-step annealed in holders of different geometry was characterized by the scanning infrared polariscope (SIRP) method. The SIRP maps reveal that the distribution of strain is significantly influenced by the symmetry of annealing, in particular by the points of contact between wafer and holder. In contrast to the as-grown state, the annealed wafers show fine patterns of slip lines. The lowest level and the most homogeneous distribution of residual strain were achieved by annealing in a vertically positioned holder of graphite rings. The radial temperature differences in the wafers caused by heating and cooling were checked by means of thermocouples on dummies of graphite. Temperature gradients up to 30 K cm−1 were measured depending upon the rates of cooling and heating.

Keywords：Annealed; GaAs wafers; Residual strain

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Pulse plating of Pt on n-GaAs (100) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation ofhν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH₃ etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered.

Source: sciencedirect

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Residual strain in annealed GaAs single-crystal wafers as determined by scanning infrared polariscopy, X-ray diffraction and topography

We have compared the strain data in GaAs wafers, as-grown as well as annealed, determined by means of the scanning infrared polariscope (SIRP) with data of high-resolution X-ray diffraction (HRXD) and qualitative results of a synchrotron based, single-crystal X-ray transmission topography (SXRTT) study. The in-plane strain component |εr−εt| measured by SIRP throughout the wafer thickness was about 10₋₅, while it derived from the single components ε_xx, ε_yy, and εxy determined by HRXD at a penetrated layer close to the surface was above 10⁻⁴. Consequently, we assume that a strong strain gradient exists between the surface and the bulk.

Source: Journal of Crystal Growth

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Characterization of EL2 distribution on semi‐insulating GaAs wafer by optically assisted imperfection profile

An improved nondestructive characterization technique is developed to measure the relative density distribution of the EL2 level in undoped semi‐insulating (SI) GaAs wafers at room temperature. Experimentally, the resistance of a small area of the wafer is measured twice, first with greater than band‐gap illumination outside a small masked area and then with a narrow‐band optical filter centered at 1074 nm in place of the masked area. The difference of the two measured resistances is shown to be proportional to the density of the EL2 level. By moving the masked area across the wafer while taking resistance measurements, the relative density variation of EL2 can be determined. A theoretical discussion based on the commonly used compensation model for undoped SI GaAs materials is presented to interpret the experimental data. A technique for applying electrical contacts to SI GaAs materials by ultrasonic soldering has been developed to achieve reproducible measurements. Although only GaAs materials were investigated, this optically assisted imperfection profile can be applied to study other high‐resistivity semiconductors.

Source:IEEE

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GaAs wafer breakage: Causes and cures, growth and process

The impact of GaAs wafer breakage on processing facilities is discussed. Wafer strength and equipment assessment are detailed. The authors describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unassignable causes. When proper material and process control techniques are used, GaAs wafer breakage should not occur.

Source:IEEE

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CW and Q-switched mode-locking of a Nd:YVO/sub 4/ laser with a GaAs wafer

Summary from only given. We demonstrate the CW mode locking in a Nd:YVO/sub 4/ laser by using a single crystal GaAs wafer as the saturable absorber as well as the output coupler. We show that by simply changing the laser power density in the GaAs wafer either a pure CW mode locking or a Q-switched mode locking can be achieved.

Source:IEEE

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The Study of Femto-Second Laser Induced Damage Threshold on Semi-Insulating GaAs Wafer

We demonstrated an experiment of femtosecond-laser damage threshold on GaAs wafer, the damage threshold was measured from 50 to 400fs. The mechanism was discussed through injection power, pulse duration and ablation profile. The results showed that the damage threshold increased with the pulse duration, the relationship between diameter of ablation hole and laser power density was also analyzed. It was concluded that the main factor affecting the damage threshold was photon ionization and collision ionization.

Source: Chao Yang Li

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Design Of Experiment (DOE) For Thickness Reduction Of GaAs Wafer Using Lapping Process

This paper report a statistical method of performing wafer lapping experimental using design of experiment (DOE) technique in order to get best lapping time to reduced thickness of GaAs wafer. Lapping speed, lapping time, oscillator speed and weight was selected as four main factor determine the shortest time of thickness reduction. A complete 2⁴ factorial of 4 factors (16 run) was design to determined the effect of selected factor. The lapping process was carried out using ULTRATEC Lapping& Polishing machine while the wafer thickness was characterized using Logitech non contact gauge. It was found that best lapping parameter was using lapping speed at 3 r.p.m, oscillator speed at 2 r.p.m and 3 weight block for duration of 240 sec. This parameter is able to reduce 156 mum of waferwithin 240 second without any crack problems and able to give good reference of reduction of GaAswafer thickness process period.

Source:IEEE

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Inductively coupled plasma reactive ion etching of GaAs wafer pieces with enhanced device yield

Inductively coupled plasma reactive ion etching (ICP-RIE) is used in the fabrication of GaAs slab-coupled optical waveguide (SCOW) laser and amplifier devices in order to prepare etched-ridge-waveguide surface features. The processing of GaAs wafer pieces (less than full wafers) requires mounting these samples on a ceramic or silicon carrier wafer by means of a thermally conductive mounting paste to improve thermal contact between the GaAs and carrier wafer. However, use of a mounting paste requires additional postetch handling of samples, including mechanical clean-up and multiple solvent cleaning steps. Insufficient paste removal can lead to unwanted surface contamination and film adhesion issues during subsequent sample processing. Massachusetts Institute of Technology Lincoln Laboratory has developed an ICP-RIE process for GaAs wafer pieces that eliminates the use of mounting paste. This process features time-limited thermal management during etching, which is essential to maintain predictable etch rates along with suitable etched surfaces and satisfactory sidewall quality. Utilizing this simplified etch process for SCOW fabrication has resulted in greatly reduced film adhesion failures and a dramatic improvement in device yield.

Source:IEEE

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Surface defects in GaAs wafer processes

The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 μm in TTV and the warp to less than 5 μm. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

Source: Journal of Crystal Growth

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Fabrication of GaAs laser diodes on Si using low-temperature bonding of MBE-grown GaAs wafers with Si wafers

We present a study of the properties of III–V structures integrated on Si by low-temperature GaAs–Si wafer bonding, using an intermediate spin-on-glass layer. Transmission electron microscopy revealed the good quality of the bonding and the absence of micro-cracks or dislocations in the semiconductor material. Photoluminescence measurements on GaAs/AlGaAs multiple quantum well structures bonded on Si confirmed that the structural integrity of the quantum wells was preserved during the wafer bonding and thinning process. Photoreflectance measurements at temperatures in the range of 80–300 K showed that the bonded GaAs layers were practically stress free at room temperature, while a tensile stress appeared at lower temperature, due to the different thermal expansion coefficients of GaAs and Si. Laser devices with etched mirrors were fabricated on silicon and exhibited similar performances with reference devices fabricated on a GaAs substrate.

Source: Journal of Crystal Growth

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Graphic script provides quick classification of GaAs wafers

Infrared transmission topography has long been used to detect variations in gallium arsenide wafers that can cause dark-line defects that limit lifetime of GaAs lasers and solar cells. In the past, infrared transmission was measured over a whole wafer by scanning a small spot mechanically. Absorption was calculated at each location across the surface of the wafer and used to produce colour-coded plots that allow the wafer's characteristics to be determined at a glance. The program ran on VAX/VMS computers, but these are being taken out of service due to obsolescence. To overcome these problems, the author developed a graphics script using a state-of-the-art data analysis program which provides quick classification of GaAs wafers based on traps and defects, but runs on inexpensive personal computers and, as a bonus, produces bit-map plots that can be cut and pasted into Windows word processing and presentation software.

Source: III-Vs Review

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Crystal growth of large-diameter bulk CdTe on GaAs wafer seed plates

We report here on some of the characteristics of CdTe bulk crystals grown on commercially available (2 1 1)B GaAs wafers by multitube physical vapour transport, a process analogous to vapour phase heteroepitaxy. Crystals several millimetres in thickness have been grown on 50 mm diameter seed plates with growth rates∼120 μm/h. Double- and triple-axis X-ray diffraction gave resolution-limited FWHM values of 34 arcsec. Maps across an as-grown surface showed the FWHM to be less than ∼80 arcsec over the majority of the surface. Infrared microscopy revealed there were comparatively low levels of Te inclusions in the central part of the crystal, but rather higher concentrations towards the edges. The use of GaAs substrates did not appear to produce the compensated material, and it was necessary to dope the material with Cl to render it semi-insulating.

Source: Journal of Crystal Growth

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Stress analysis and bending tests for GaAs wafers

Wafer made from single crystal gallium arsenide (GaAs) are used as substrate materials in micro- and opto-electronic devices. During the various processes of manufacturing, the wafers are subjected to mechanical loads which may lead to fracture. The characterization of the fracture strength of the wafers need bending tests and a theoretical calculation of various stress distributions within the wafers.

In this study we show that the nonlinear von Kármán theory may serve as an appropriate tool to calculate the stress distributions as functions of the external load, while the Kirchhoff theory has turned out to be completely inappropriate. Our main focus is devoted to (i) calculation of the contact area between the load sphere and the wafer, (ii) study of the influence of the anisotropic character of the material, (iii) study of the important geometric nonlinearity. Finally we compare the calculated and theoretical load–flexure relations in order to demonstrate the high accuracy of the von Kármán theory and its finite element implementation.

Source:Microelectronics Reliability

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State of the art 6″ SI GaAs wafers made of conventionally grown LEC-crystals

6″ SI GaAs single crystals are grown by the standard LEC-process in a new-generation multi-heater puller designed for charges up to 50 kg and crucibles up to 12″, applying the carbon controlled growth technology. It is demonstrated that the increasing requirements of device manufacturers with regard to macroscopic and mesoscopic homogeneity of electrical properties, mechanical strength, flatness and cleanliness of the wafers can be fully met by LEC grown 6″ crystals.

Source:Journal of Crystal Growth

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Optimization of gas flow and etch depth uniformity for plasma etching of large area GaAs wafers

1. Introduction

Mass production of GaAs-based advanced devices accelerates wafer scale-up and process optimization. Those devices include such as GaAs/AlGaAs or GaAs/InGaP metal semiconductor field effect transistors (MESFET), heterojuncton bipolar transistors (HBT)  and high electron mobility transistors (HEMT). Recently, GaAs device industries try to increase its volume with processing of large size wafers such as 100 and 150 mm diameters. Especially, it is currently a transition time from 100 mm (4 in.) to 150 mm (6 in.) in mass-production of MESFET and HBT industries. It means that most of GaAs-based processes have to be ready for scale-up.

One of critical issues of dry etching of such a large GaAs wafer is to maintain a good uniformity. It is a key issue to make it possible to preserve the process uniformity in a large area GaAs wafer. Another issue for high productivity during GaAs etching is to minimize edge exclusion on a wafer. In advanced GaAs industries, the edge exclusion is getting tighter than ever. The limit for edge exclusion currently revolves from 8–10 to 4–6 mm. Minimization of edge exclusion can improve efficiency of throughput after dry etch processes.

Compactness of the reactor is also an important issue for business and maintenance point of view in industry. If the reactor is inadequately big for a certain size wafer processing without optimization, it wastes extra cost for expense. The chamber will require expensive vacuum pumps, which are bigger than it needs. It will also require more gas flow in order to maintain a given pressure than an optimized chamber will do.

The issue is now clear. It is how to improve the etch depth distribution on a wafer during plasma etching in a compact chamber. One of basic information that we want to know is to understand effect of gas flow distribution to that of etch depth in the chamber. In our previous experiment, it was found that the etch depth on GaAs wafer was generally higher at the edge and low at the center after plasma etching in both selective and non-selective ICP etching when the gas inserted from the edge of a reactor. Our curiosity goes to try to understand “Is there any geometrical effect in order to improve the dry etch uniformity?” and “How to optimize clamp design for uniform plasma etching if a reactor size is already fixed?”

In this paper, we will discuss about how to improve the gas flow uniformity in a chamber. Both simulation and experimental data showed that it was possible to have optimized chuck and electrode design for excellent gas flow in a reactor. It was also understood that size and height of clamp and focus ring significantly affected gas flow uniformity, etch depth topography and etch depth uniformity, finally.

2. Experimental

A finite difference numerical method was used for gas flow simulation. A chamber was designed as 300 mm diameter and 300 mm height. A chuck was designed as 200 mm diameter and 150 mm height in the simulation. Several clamps and focus rings with different sizes and heights were introduced in the simulation. Plasma gases could be inserted through center, edge or a showerhead in the calculation. Simulation was done for both 100 mm (4 in.) and 150 mm (6 in.) diameter GaAs wafers.

A few simulated data was compared to real experiment results acquired with an ICP etching system. BCl₃/N₂/SF₆/He gas was used for GaAs etching. Full-size 100 mm GaAs wafers were used to collect the etch depth data as a function of focus ring height for comparison of the data.

3. Results and discussion

Fig. 1 shows simulated gas flow uniformity as a function of wafer diameter on the electrode. It is noticed that flow distribution by gas insertion from the edge has a similar trend to that through a shower head over the wafer. The results depicted that gas flow distribution was always high at the edge and low at the center if gas was introduced through either edge of the reactor or showerhead over the wafer. However, it was noticed that the gas insertion from the center could change the trend of gas flow distribution on the wafer. A reverse result of gas flux (i.e. high at the center and low at the edge) was obtained by changing the position of gas insertion in the chamber. Gas flow uniformity could be poor as high as ±25% in any condition with the model reactor. Width of the reactor was 300 mm and height of the electrode was 150 mm in the simulation model. No clamp on the electrode was assumed for the data on the Fig. 1.

Fig. 1. Gas flow uniformity as a function of distance from an edge on 150 mm wafer (without a clamp).

Fig. 2 shows simulation result on an effect of a 0.5 cm thick clamp for gas flow distribution in the reactor for 150 mm GaAs wafer processing. Introduction of a clamp in order to fix a wafer could affect the gas flow. Further simulation indicated that height of the clamp and size of the clamp were also important to control gas flow distribution on the wafer in the chamber. According to Fig. 2, the introduction of clamp helped improve the gas flux uniformity by reduction of peak height for gas flow near the clamp if the gas inserted from a showerhead or edge. However, it would make it worse if the gas came into the chamber from the center of the top electrode.

Fig. 2. Gas flow uniformity as a function of distance from an edge on 150 mm wafer (with a clamp).

Simulated data for gas flow uniformity on a 100 mm diameter wafer was shown on Fig. 3. The gas was inserted from the edge of the reactor. The clamp was on the position in the simulation. According to the results, uniformity of gas flow distribution was ±6% and gas flow was higher at the edge than at the center. Note that introduction of a focus ring around the wafer could decrease gas flow uniformity. The data also confirmed that optimized configuration existed with the fixed size and height of the clamp on the electrode. If the focus ring was too high, it made the uniformity worse.

Fig. 3. Gas flow uniformity as a function of distance from an edge on 100 mm wafer (with a clamp).

The simulation results were compared with experimental data. Comparison of Fig. 3 and Fig. 4 indicated that the simulation of gas flow distribution matched very well for etch depth uniformity for GaAs etching. The etching gas of GaAs (BCl₃/N₂/SF₆/He) was inserted from the edge in the experiment. Different height of dielectric-based focus rings was introduced in sequential runs. The results showed that etch depth distribution exactly resembled those of gas flow, i.e. optimized height of focus ring existed in order to achieve minimum etch uniformity. A main role of the focus ring was to control the gas flow distribution in the chamber.Fig. 4 showed that the etch uniformity could be significantly improved by optimization of clamp and focus ring configuration.

Fig. 4. Etch depth distribution of GaAs as a function of distance from an edge on 100 mm GaAs wafer after inductively coupled BCl₃/N₂/SF₆/He plasma etching (with a clamp).

Fig. 5 shows gas flow uniformity as a function of clamp size. A best configuration was achieved with a gas insertion through a showerhead in the simulation. According to the result, the gas flow uniformity varies as a function of clamp size as well as the height of the clamp even though the dimension of reactor and electrode were fixed. Notice that the lowest uniformity existed with a 1 cm distance from the wafer in the reactor. Clamp thickness was fixed as 0.5 cm in the simulation. Therefore, it meant that the height of clamp up to 1 cm from the wafer edge should be as low as wafer thickness in order to achieve excellent uniformity. The results showed that the flow uniformity could be reduced as low as <±1.5% up to the very edge (<2 mm) of the wafer.

Fig. 5. Gas flow uniformity as a function of distance from an edge on 100 mm wafer (with both a clamp and a showerhead).

Gas flow distribution on 150 mm (6 in.) diameter GaAs wafer was simulated at the same chamber and electrode with gas insertion through a showerhead (Fig. 6). According to the result, gas flow distribution could be as low as ±3% with the wafer. It increased from ±1.5% with a 100 mm diameter wafer. However, the data was still quite good. If etch depth distribution follows same trends in 150 mm wafer processing too, it is expected to have about 3% etch depth uniformity up to very edge (<3 mm) of the 150 mm wafer. The simulation results showed that 300 mm width of chamber could handle 150 mm wafer with a quite good gas flow uniformity.

Fig. 6. Gas flow uniformity as a function of distance from an edge on 150 mm wafer (with both a clamp and a showerhead).

4. Summary and conclusions

We compared simulated gas flow uniformity with experimental data of etch depth distribution for dry etching of large area GaAs wafer. The results showed that etch depth trends of GaAs in BCl₃/N₂/SF₆/He followed the trace of gas flow distribution simulated by finite difference numerical method. It was confirmed that advanced design of gas flow distribution in a reactor was very important to have excellent etch depth uniformity for a large area GaAs wafer in plasma etching. Introduction of an optimized clamp and a focus ring could help achieve great uniformity on the wafer for BCl₃/N₂/SF₆/He plasma etching of GaAs wafer.

Source: Solid-State Electronics

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2K PL topography of silicon doped VGF GaAs wafers

We report on full wafer and small area photoluminescence topography investigations of VGF GaAs:Si wafers. The wavelength-specific images exhibit various correlations and anti-correlations. Intensity variations due to competitive radiative and non-radiative recombination processes are mainly due to stoichiometric fluctuations and can be distinguished from those generated by the variation of the silicon dopant concentration. X-ray transmission topograms allow to identify grown-in defects like precipitates and dislocations and to correlate these with the observed macro- and microscopic luminescence variation patterns.

Source: Materials Science and Engineering: B

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Thermal processing induced plastic deformation in GaAs wafers

Different types of dislocation bundles were identified in the (001) GaAs substrates of III–V heterostructures. Comparisons of scanning infrared polariscopy images and X-ray transmission topograms showed a one to one correlation of stripes of reduced residual shear strain and dislocation bundles of the majority type. Visible-light interferometry and Makyoh topography, on the other hand, showed a slip-line distribution that is in correspondence to the distribution of dislocation bundles of the minority type(s). A new model for the plastic deformation of circular GaAs wafers during thermal processing is briefly outlined and its good agreement with the main experimental results demonstrated.

Source:Materials Science and Engineering: B

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