Apr 13, 2020

Quantitative Analysis of the Metallic Contamination On GaAs and InP Wafers by TXRF and ICPMS Techniques

The quantitative analysis of the metallic contaminants both by chemical collection coupled to ICPMS and TXRF were implemented on GaAs and InP 100mm wafers. VPD-DC-ICPMS and LPD-ICPMS were developed respectively for GaAs and InP substrates. These methods present CE higher than 85% for usual metallic contaminants except for Cu & noble metals, and very sensitive detection thresholds are reached (108 to 1011 at/cm²). TXRF analysis conditions were optimized on both substrates. Na, Mg, Al, Ir and Ge on GaAs and K, Ca, Pd and Ag on InP are not analyzable due to substrate interferences. TXRF calibration was carried out from intentionally contaminated wafers in reference to ICPMS methods. Finally, TXRF enables to reach interesting detection limits (1010 to 1012at/cm² range) and is able to measure Cu and some noble metals.

Source:IOPscience

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Apr 6, 2020

Fabrication of GaAs-on-Insulator via Low Temperature Wafer Bonding and Sacrificial Etching of Ge by XeF2

Front end integration of III-V compound semiconductor devices with Si complimentary metal-oxide-semiconductor (CMOS) technology requires the development of commercially viable engineered substrates. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding and layer exfoliation. In this paper we report on the development of GaAs-on-insulator (GaAsOI) structures without the use of Smart Cut technology. Epitaxial GaAs/Ge/GaAs stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding. A room temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate was realized through room temperature, gas-phase lateral etching of the embedded Ge sacrificial layer by exposure to xenon difluoride (XeF2). This GaAsOI fabrication process is shown to be successful on a small scale, though implementation for the production of commercially-viable large area GaAsOI substrates at full wafer scale is currently limited by the long gas transport distance associated with a wafer-scale lateral etching process. In order to explore possibilities for overcoming this limitation we established a model that identifies the rate limiting processes and discuss potential approaches that will allow for the implementation of our gas phase lateral etching process for the fabrication of large diameter GaAsOI substrates.

Source:IOPscience

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Mar 29, 2020

Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal–oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits.

Source:IOPscience

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Mar 24, 2020

Arsenic Formation on GaAs during Etching in HF Solutions: Relevance for the Epitaxial Lift-Off Process

The epitaxial lift-off (ELO) process is utilized to produce thin-film III-V devices, while the substrate (GaAs wafer) on which the III-V structure was grown can be reused. However, so far the direct reuse of these GaAs wafers is inhibited by the remnants on the wafer surface that cannot be removed in a straightforward fashion utilizing general cleaning methods. Therefore, etching of GaAs wafers in hydrofluoric acid was investigated by microscopic techniques, profilometry and X-ray photoelectron spectroscopy. It was found that immediately after etching the wafer surface is covered by a brown layer of elemental arsenic. The thickness and uniformity of this layer depend on both illumination during etching and the HF concentration. During storage of the etched wafer the As layer is replaced by As2O3 particles. It is shown that oxide particles form only when the wafer is exposed to light in the presence of air. A model that explains the As formation and the subsequent particle formation is given.

Source:IOPscience

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Mar 17, 2020

Optical Investigations of Directly Wafer-Bonded InP–GaAs Heterojunctions

The optical characteristics of directly wafer-bonded InP–GaAs heterojunctions have been investigated. By designing the bonding interface at standing-wave antinode, its influence on optical performances of bonded structures is magnified, which facilitates experimental detection using optical methods. Wavelength blueshift and reflectivity falling at the resonance mode were observed in wafer-bonded InP–GaAs heterostructures. Numerical analysis suggests that two effects involving thickness change of interfacial bonding layers and extra optical loss introduced by bonded junctions are responsible for the experimental observations, and these effects can be attenuated by lowering anneal temperatures and incorporating an  superlattice into the surface of InP-based materials. The results are useful for designing effective optical characteristics of wafer-bonded device structures.

Source:IOPscience

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Mar 10, 2020

Room temperature contactless electroreflectance characterization of InGaAs/InAs/GaAs quantum dot wafers

Contactless electroreflectance (CER) mapping has been performed on InGaAs capped InAs/GaAs quantum dot (QD) wafers of 2 inch diameter grown by molecular beam epitaxy. The CER spectra have revealed several features related to InAs self-assembled QDs and a quantum well (QW) formed of the InAs wetting layer and the InGaAs cap layer. The particular optical transitions have been identified based on theoretical calculations of the energy levels in the InAs/InGaAs/GaAs wetting layer related step-like QW, performed within the effective mass approximation. The influence of possible uncertainties in cap content or band offsets has also been analysed. The advantages of modulation spectroscopy, namely its absorption-like character and high sensitivity to optical transitions with even very low oscillator strength including those between the excited states, have allowed the energies of all the transitions along the wafer to be followed. The latter has shown that within experimental error the transition energies are independent of the position of the probing spot on the sample. It demonstrates not only a very high uniformity of the dot ensemble but also the wetting layer related QW and hence also the content and thickness of the InGaAs cap.

Source:IOPscience

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Mar 5, 2020

Bonding of Elastically Strain-Relaxed GaAs/InGaAs/GaAs Heterostructures to GaAs(001)

Bonding of elastically strain-relaxed GaAs/InGaAs/GaAs heterostructures has been achieved on GaAs(001) substrates by the method of in-place bonding. Pseudomorphic heterostructures were patterned and a sacrificial AlAs layer was removed by selective etching. As etching proceeds and the GaAs/InGaAs/GaAs structure is released from the substrate, elastic strain relaxation occurs and the strain-relaxed structures are weakly bonded in-place to the substrate. The bond between the strain-relaxed structure and the substrate was then strengthened by annealing under conditions similar to those used for whole wafer bonding of GaAs. The degree of strain relaxation of the InGaAs layer is determined by the relative thickness of the GaAs and InGaAs layers. The increase in the in-plane lattice parameter of these bonded GaAs/InGaAs/GaAs structures is 0.3-0.4%.

Source:IOPscience

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Feb 25, 2020

(Invited) (ECS Electronics & Photonics Division Award )Wafer-Level Step-Stressing of InGaP/GaAs HBTs

Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where base-emitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level step-stress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.

Source:IOPscience

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Feb 19, 2020

A Cross‐Hatch Pattern in GaAs1 − x  P  x Epitaxially Grown on GaAs Substrate

A cross‐hatch pattern which appears on the surface of  epitaxially grown on the substrate was studied by x‐ray diffraction techniques. The origin of this structure was determined by x‐ray diffraction topography to be a misfit dislocation array aligned along lines perpendicular to each other in the layer of graded composition. The composition profile normal to the wafer was also determined by electron microprobe analyses. Furthermore, the growth mechanism of the aligned dislocations was proposed from the fact that aligned dislocations enable a considerable reduction in the curvature of the wafer which is due to the lattice mismatch between the  epitaxial layer and the  substrate. The  wafer having the cross‐hatch pattern was determined to be high in quality from the half width of the rocking curve.

Source:IOPscience

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Feb 12, 2020

Interface Morphology Investigation of Bonded p-GaAs/p-Si Wafers

The integration of GaAs and Si can combine the superior electrical and optical properties of GaAs with the mechanical and economical advantages of Si. It presents great potential for OEICs applications. In this study, direct wafer bonding was applied to combine bulk p-Si and p-GaAs. Interface morphologies of bonded p-GaAs/p-Si wafers were investigated by TEM.

Source:IOPscience

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Jan 20, 2020

Fast Atom Beam Activated Wafer Bonds between n-Si and n-GaAs with Low Resistance

Fast atom beam activated direct wafer bonds can be used to combine GaAs and Si semiconductor structures and to achieve high bond strength and optical transparency. Some applications require a low ohmic resistance between the materials. Therefore, IV-characteristics of n-type wafer bonds between n-Si and n-GaAs were thoroughly investigated. n-Si/n-Si bonds showed ohmic resistance below 2.5 × 10−3 Ωcm2. However diode like IV-curves were found for both n-GaAs/n-GaAs and n-Si/n-GaAs bonds. This can be explained by the formation of a potential barrier at the interface, caused by carrier trapping in fast atom beam induced defects. Hall measurements of n-GaAs after fast atom beam treatment confirmed both, a reduction of the active carrier concentration, and the electron mobility. It was found that thermal annealing and higher bond temperatures can help reducing the potential barrier height at the n-Si/n-GaAs interface and thus lower the electrical bond resistance by healing crystalline defects. Highly conductive n-Si/n-GaAs wafer bonds with an interface resistance below 3.6 × 10−3 Ωcm2 were achieved after the optimization.

Source:IOPscience

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Jan 13, 2020

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Source:IOPscience


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Jan 7, 2020

Interfacial and mechanical characterization of wafer-bonded GaSb/amorphous α-(Ga,As)/GaAs structure for GaSb-on-insulator applications

In this study, the feasibility of using wafer-bonding technology to fabricate a GaSb semiconductor on GaAs substrates for potentially creating a GaSb-on-insulator structure has been demonstrated. A GaSb wafer has been bonded on two types of GaAs substrates: (1) a regular single crystal semi-insulating GaAs substrate and (2) the GaAs wafers with pre-deposited low-temperature amorphous α-(Ga,As) layers. The microstructures and interface adhesion studies have been carried out on these wafer-bonded semiconductors. It has been found that the GaSb-on-α-(Ga,As) wafers have shown enhanced interface adhesion and lower temperature bonding capability.

Source:IOPscience

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Electrical Conductivity of Direct Wafer-Bonded GaAs/GaAs Structures for Wafer-Bonded Tandem Solar Cells

Wafer bonding of GaAs using an ammonium sulfide (NH4)2S treatment is investigated for various structures. The effect of the wafer offcut angle on the electrical conductivity of III-V solar cell devices using n-GaAs/n-GaAs wafer-bonded structures is studied. High resolution x-ray diffraction is used to confirm the misorientation of the bonded samples. Additionally, we compare the electrical properties of epitaxially grown p-n junctions on GaAs to n-GaAs/p-GaAs wafer-bonded structures. High resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM) are used to compare the interface morphology across the range of relative misorientations after a 600 {degree sign}C RTP. The ratio of well-bonded crystalline regions to amorphous oxide inclusions is consistent across all bonded samples, indicating that the degree of misorientation does not affect the level of interface recrystallization at high temperatures.

Source:IOPscience

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