(Invited) (ECS Electronics & Photonics Division Award )Wafer-Level Step-Stressing of InGaP/GaAs HBTs

Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where base-emitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level step-stress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.

Source:IOPscience

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A Cross‐Hatch Pattern in GaAs1 − x P x Epitaxially Grown on GaAs Substrate

A cross‐hatch pattern which appears on the surface of  epitaxially grown on the substrate was studied by x‐ray diffraction techniques. The origin of this structure was determined by x‐ray diffraction topography to be a misfit dislocation array aligned along lines perpendicular to each other in the layer of graded composition. The composition profile normal to the wafer was also determined by electron microprobe analyses. Furthermore, the growth mechanism of the aligned dislocations was proposed from the fact that aligned dislocations enable a considerable reduction in the curvature of the wafer which is due to the lattice mismatch between the  epitaxial layer and the  substrate. The  wafer having the cross‐hatch pattern was determined to be high in quality from the half width of the rocking curve.

Source:IOPscience

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Interface Morphology Investigation of Bonded p-GaAs/p-Si Wafers

The integration of GaAs and Si can combine the superior electrical and optical properties of GaAs with the mechanical and economical advantages of Si. It presents great potential for OEICs applications. In this study, direct wafer bonding was applied to combine bulk p-Si and p-GaAs. Interface morphologies of bonded p-GaAs/p-Si wafers were investigated by TEM.

Source:IOPscience

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