Dec 25, 2019

Determination of Shallow Acceptor Concentration in  SI  ‐ GaAs from Steady‐State and Transient Microwave Photoconductivity Measurements

A non‐destructive characterization method using microwaves has been employed to determine the shallow acceptor concentration in undoped LEC semi‐insulating gallium arsenide  wafers. Both the above‐bandgap steady‐state and the below‐bandgap transient photoconductivities of  wafers are measured using a Ka‐band reflection‐type microwave setup in which there is no need to fabricate electrical contacts on  wafers. A photoconductivity model adopted from the two‐energy‐level defect model for undoped LEC semi‐insulating  is used to derive the relationship between the photoinduced microwave response and the concentration of shallow acceptors, mainly carbon. In the above‐ bandgap photoconductivity measurement, it is found that the steady‐state microwave response is inversely proportional to the square root of the shallow acceptor concentration. In the below‐bandgap photoconductivity measurement, the transient microwave response shows an initial fast decay and a second slower decay which has a Na‐related decay time constant. More than 30 undoped LEC  bulk wafers were used in our measurements to establish the correlation. These wafers have a carbon concentration ranging from  to , determined by LVM infrared absorption. Good agreements have been found between the shallow acceptor concentration obtained from the microwave photoconductivity measurements and the LVM carbon concentration.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Dec 18, 2019

Improved GaAs Bonding Process for Quasi‐Phase‐Matched Second Harmonic Generation

A multilayer stack of bonded GaAs wafers, each layer rotated 180° from the adjacent one, has been proposed for quasi‐phase‐matched second harmonic generation. Current bonding technology, however, often leads to unacceptable optical losses and, therefore, poor device performance. In this study, three sources of optical losses were investigated: (i) interfacial defects between the wafers, (ii) bulk defects within the wafers, and (iii) decomposition at the exposed outer surfaces. Surface losses due to incongruent evaporation were easily eliminated by repolishing the outer surfaces. However, to minimize the losses from interfacial and bulk defects, it was necessary to investigate the relationship between these defects and the processing parameters. It was found that an increase in temperature and/or time led to a decrease in interfacial defects, but an increase in bulk and surface defects. Optimized processing conditions were developed which permit the preparation of stacks containing over 50 layers of (100) GaAs wafers, and about 40 layers of (110) GaAs wafers. Optical losses as low as 0.1 to 0.3 % per interface (at 5.3 and 10.6 μm) were observed for the (110) oriented multilayer structures.

Source:IOPscience
For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Dec 11, 2019

In Situ Surface Treatment of GaAs ( 100 )  Wafer in Metal Salt Electrolytes for Fabrication of Schottky Contact

The electrochemical behavior of n‐type  was investigated to find an optimum condition for in situsurface treatment in Ni salt electrolytes prior to the fabrication of  Schottky contacts by the wet method. Commercial machine‐polished  wafers with damaged crystal lattices did not show photoresponse and behaved exactly the same as a Ga metal electrode in the region of −0.1 to +0.5 V vs. . Photoresponse was observed after the removal of the damaged surface layer in . The in situsurface treatment of  was done by photoelectrochemical etching at +0.1 V in acidic nickel salt electrolyte followed by the fabrication of a  Schottky contact by applying negative potentials. Comparison of the fabrication methods is summarized in a table. The wet method is recommended for the fabrication of a  Schottky contact.

Source:IOPscience
For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Dec 4, 2019

Wafer-scale processing technology for monolithically integrated GaSb thermophotovoltaic device array on semi-insulating GaAs substrate

This paper presents the entire fabrication and processing steps necessary for wafer scale monolithic integration of series interconnected GaSb devices grown on semi-insulating GaAs substrates. A device array has been fabricated on complete 50 mm (2 inch) diameter wafer using standard photolithography, wet chemical selective etching, dielectric deposition and single-sided metallization. For proof of concept of the wafer-scale feasibility of this process, six large-area series interconnected GaSb p–n junction thermophotovoltaic cells with each cell consisting of 24 small-area devices have been fabricated and characterized for its electrical connectivity. The fabrication process presented in this paper can be used for optoelectronic and electronic device technologies based on GaSb and related antimonide based compound semiconductors.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Nov 27, 2019

Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Nov 19, 2019

Direct-bonded four-junction GaAs solar cells*

Direct wafer bonding technology is able to integrate two smooth wafers and thus can be used in fabricating III–V multijunction solar cells with lattice mismatch. In order to monolithically interconnect between the GaInP/GaAs and InGaAsP/InGaAs subcells, the bonded GaAs/InP heterojunction must be a highly conductive ohmic junction or a tunnel junction. Three types of bonding interfaces were designed by tuning the conduction type and doping elements of GaAs and InP. The electrical properties of p-GaAs (Zn doped)/n-InP (Si doped), p-GaAs (C doped)/n-InP (Si doped) and n-GaAs (Si doped)/n-InP (Si doped) bonded heterojunctions were analyzed from the I–V characteristics. The wafer bonding process was investigated by improving the quality of the sample surface and optimizing the bonding parameters such as bonding temperature, bonding pressure, bonding time and so on. Finally, GaInP/GaAs/InGaAsP/InGaAs 4-junction solar cells have been prepared by a direct wafer bonding technique with the high efficiency of 34.14% at the AM0 

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Nov 11, 2019

Doubly passively Q-switched Nd:GGG laser with a monolayer graphene saturable absorber and GaAs wafer

A doubly passively Q-switched Nd:GGG laser with monolayer graphene and GaAs wafer working as saturable absorbers is presented, in which the GaAs wafer also works as the output coupler. At the maximum incident pump power of 7.69 W, the obtained output power, the pulse duration and the pulse repetition rate are 820 mW, 1.06 ns, and 21.5 kHz, respectively, corresponding to pulse energy of 38.2 μJ and peak power of 35.9 kW, respectively.

Source:IOPscience


For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Nov 6, 2019

Interfacial and mechanical characterization of wafer-bonded GaSb/amorphous α-(Ga,As)/GaAs structure for GaSb-on-insulator applications

In this study, the feasibility of using wafer-bonding technology to fabricate a GaSb semiconductor on GaAs substrates for potentially creating a GaSb-on-insulator structure has been demonstrated. A GaSb wafer has been bonded on two types of GaAs substrates: (1) a regular single crystal semi-insulating GaAs substrate and (2) the GaAs wafers with pre-deposited low-temperature amorphous α-(Ga,As) layers. The microstructures and interface adhesion studies have been carried out on these wafer-bonded semiconductors. It has been found that the GaSb-on-α-(Ga,As) wafers have shown enhanced interface adhesion and lower temperature bonding capability.

Source:IOPscience
For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Oct 29, 2019

Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

The electrical properties of room-temperature bonded wafers made from materials with different lattice constants, such as p-GaAs and n-Si, p-GaAs and n-Si [both with an indium tin oxide (ITO) surface layer], and n-GaN and p-GaAs, were investigated. The bonded p-GaAs//n-Si sample exhibited an electrical interface resistance of 2.8 × 10−1 Ωcenterdotcm2 and showed ohmic-like characteristics. In contrast, the bonded p-GaAs/ITO//ITO/n-Si sample showed Schottky-like characteristics. The bonded n-GaN//p-GaAs wafer sample exhibited ohmic-like characteristics with an interface resistance of 2.7 Ωcenterdotcm2. To our knowledge, this is the first reported instance of a bonded GaN//GaAs wafer with a low electrical resistance.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Aug 21, 2019

Comparison of self-assisted VLS GaAs nanowires grown by MBE on Si (111) and GaAs (111)B substrates

In this work GaAs nanowires were grown by self-assisted growth method with completely identical growth parameters, such as growth temperature, growth time, Ga and As flux, on GaAs (111)B and Si (111) substrates using Molecular Beam Epitaxy (MBE). All samples were then characterized by Scanning Electron Microscope (SEM), Energy-dispersive X-ray spectroscopy (EDX), and X-ray Diffraction (XRD). The results from both substrates were compared in order to understand the effect of substrate type on nanowires.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Aug 16, 2019

Highly efficient photoconductive antennas using optimum low-temperature-grown GaAs layers and Si substrates

We have improved the efficiency of photoconductive antennas (PCAs) using low-temperature-grown GaAs (LT-GaAs). We found that the physical properties of LT-GaAs photoconductive layers greatly affect the generation and detection characteristics of terahertz (THz) waves. In THz generation, high photoexcited carrier mobility and the presence of a few As clusters in the LT-GaAs are two important factors. In detection, short carrier lifetime and the absence of a polycrystalline structure in the LT-GaAs are significant factors. By optimizing these physical properties, we improved the total dynamic range of THz generation and detection by 15 dB over that obtained by conventional commercially available PCAs. In addition, we replaced the semi-insulating GaAs (SI-GaAs) substrate with a Si substrate, which has a low absorption in the THz region. We proposed a new idea of including a highly insulating Al0.5Ga0.5As buffer layer on the Si substrate. Finally, we confirmed the feasibility of manufacturing PCAs using Si substrates.

Source:IOPscience


For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Aug 9, 2019

InGaAs quantum dots grown on B-type high index GaAs substrates: surface morphologies and optical properties

We systematically investigated the correlation between morphological and optical properties of InGaAs self-assembled quantum dots (QDs) grown by solid-source molecular beam epitaxy on GaAs (n 11)B (n = 9, 8, 7, 5, 3, 2) substrates. Remarkably, all InGaAs QDs on GaAs(n 11)B under investigation show optical properties superior to those for ones on GaAs(100) as regards the photoluminescence (PL) linewidth and intensity. The morphology for growth of InGaAs QDs on GaAs (n 11)B, where n = 9, 8, 7, 5, is observed to have a rounded shape with a higher degree of lateral ordering than that on GaAs(100). The optical property and the lateral ordering are best for QDs grown on a (511)B substrate surface, giving a strong correlation between lateral ordering and PL optical quality. Our results demonstrate the potential for high quality InGaAs QDs on GaAs(n 11)B for optoelectronic applications.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Aug 1, 2019

Dark current characteristics of GaAs-based 2.6 µm InGaAs photodetectors on different types of InAlAs buffer layers

GaAs-based In0.83Ga0.17As photodetectors (PDs) with cut-off wavelengths up to 2.6 µm are demonstrated. The effects of continuously-graded or fixed-composition InAlAs buffers on the device performances are investigated. The dark current characteristics of the PDs at various temperatures are analysed in detail. The photocurrents are also measured at 300 K; the detectivity of the PDs is extracted. The two GaAs-based PDs with different buffer schemes show different temperature-dependent dark current behaviours. The around room temperature performances of the GaAs-based device on the fixed-composition buffer are not as good, but comparable to those of InP-based devices, revealing a promising candidate for the GaAs-based PDs and focal plane arrays for many low-end applications.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jul 23, 2019

Titanium/Gold Schottky Contacts on P-Type GaAs Grown on (111)A and (100) GaAs Substrates Using Molecular Beam Epitaxy

The Schottky barrier heights of Ti/Au contacts on p-type GaAs, grown on (111)A and (100) GaAs substrates by molecular beam epitaxy, have been investigated by I-V and C-V techniques. Higher barrier heights are observed for contacts on (111)A GaAs films. Comparison between our results and the ideal Schottky barrier height for Ti on p-type GaAs shows that Ti/Au barrier heights on p-type (111)A GaAs films are closer to the ideal case than the Ti/Au barrier heights on p-type (100) GaAs films. This suggests that the defect densities of the Ti-GaAs interfaces of Ti/Au contacts on (111)A GaAs films are lower than those of identical Ti/Au contacts on (100) GaAs films.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jul 17, 2019

Electrical properties of Si-doped GaAs layers grown on (411)A GaAs substrates by molecular beam epitaxy

Electrical properties of Si-doped GaAs layers grown on (411)A GaAs substrates by molecular beam epitaxy (MBE) were investigated for applications to GaAs/AlGaAs resonant tunnelling diodes with atomically flat (411)A GaAs/AlGaAs interfaces over an entire device area. These flat interfaces can be realized by MBE under certain growth conditions (growth temperature Ts=580°C and V/III pressure ratio of less than or equal to 11). When the V/III pressure ratio is high (above 15) for Ts=580°C, Si-doped GaAs on a (411)A substrate showed an n-type conduction similar to conventional Si-doped GaAs on (100) substrates. (411)A GaAs/AlGaAs interfaces grown under this condition, however, cannot become as flat and as superior as conventional (100) GaAs/AlGaAs interfaces. On the other hand, when the V/III pressure ratio is 7, an Si-doped GaAs layer on (411)A showed p-type conduction. In the case of a V/III pressure ratio of 10.5 and Ts=580°C, Si-doped GaAs still showed n-type conduction with the compensation ratio ν ((ND+NA)/(ND-NA)) = 2.3. This result suggests that Si can be used as an n-type dopant in GaAs for GaAs/AlGaAs resonant tunnelling diodes grown on (411)A GaAs substrates with atomically flat (411)A GaAs/AlGaAs interfaces.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jul 9, 2019

Structural and optical characterization of GaAs nano-crystals selectively grown on Si nano-tips by MOVPE

We present the nanoheteroepitaxial growth of gallium arsenide (GaAs) on nano-patterned silicon (Si) (001) substrates fabricated using a CMOS technology compatible process. The selective growth of GaAs nano-crystals (NCs) was achieved at 570 °C by MOVPE. A detailed structure and defect characterization study of the grown nano-heterostructures was performed using scanning transmission electron microscopy, x-ray diffraction, micro-Raman, and micro-photoluminescence (μ-PL) spectroscopy. The results show single-crystalline, nearly relaxed GaAs NCs on top of slightly, by the SiO2-mask compressively strained Si nano-tips (NTs). Given the limited contact area, GaAs/Si nanostructures benefit from limited intermixing in contrast to planar GaAs films on Si. Even though a few growth defects (e.g. stacking faults, micro/nano-twins, etc) especially located at the GaAs/Si interface region were detected, the nanoheterostructures show intensive light emission, as investigated by μ-PL spectroscopy. Achieving well-ordered high quality GaAs NCs on Si NTs may provide opportunities for superior electronic, photonic, or photovoltaic device performances integrated on the silicon technology platform.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jul 5, 2019

A bow-tie photoconductive antenna using a low-temperature-grown GaAs thin-film on a silicon substrate for terahertz wave generation and detection


This paper presents heterogeneously integrated bow-tie emitter–detector photoconductive antennas (PCAs) based on low-temperature grown-gallium arsenide (LTG-GaAs) thin-film devices on silicon-dioxide/silicon (SiO2/Si) host substrates for integrated terahertz (THz) systems. The LTG-GaAs thin-film devices are fabricated with standard photolithography and thermal evaporation of metal-contact layers of chromium (Cr), nickel (Ni) and gold (Au). They are etched selectively and separated from their growth GaAs substrate. The LTG-GaAs thin-film devices are then heterogeneously integrated on bow-tie antenna electrodes patterned on the surface of a SiO2/Si host substrate for THz emitters and THz detectors. Cost-effective and selective integration of LTG-GaAs thin-film devices on a Si platform is demonstrated. THz radiation from the fabricated THz PCAs is successfully measured using a pump–probe THz time-domain configuration. The THz temporal duration was measured at full width half maximum of 0.36 ps. Its frequency spectrum exhibits a broadband response with a peak resonant frequency of about 0.31 THz. The demonstration illustrates the feasibility of creating heterogeneously integrated THz systems using separately optimized LTG-GaAs devices and Si based electronics.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jun 20, 2019

Gallium arsenide (GaAs) island growth under SiO2 nanodisks patterned on GaAs substrates

We report a growth phenomenon where uniform gallium arsenide (GaAs) islands were found to grow underneath an ordered array of SiO2 nanodisks on a GaAs(100) substrate. Each island eventually grows into a pyramidal shape resulting in the toppling of the supported SiO2 nanodisk. This phenomenon occurred consistently for each nanodisk across a large patterned area of ~ 50 ×50 µm2 (with nanodisks of 210 nm diameter and 280 nm spacing). The growth mechanism is attributed to a combination of 'catalytic' growth and facet formation.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jun 14, 2019

Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

The electrical properties of room-temperature bonded wafers made from materials with different lattice constants, such as p-GaAs and n-Si, p-GaAs and n-Si [both with an indium tin oxide (ITO) surface layer], and n-GaN and p-GaAs, were investigated. The bonded p-GaAs//n-Si sample exhibited an electrical interface resistance of 2.8 × 10−1 Ωcenterdotcm2 and showed ohmic-like characteristics. In contrast, the bonded p-GaAs/ITO//ITO/n-Si sample showed Schottky-like characteristics. The bonded n-GaN//p-GaAs wafer sample exhibited ohmic-like characteristics with an interface resistance of 2.7 Ωcenterdotcm2. To our knowledge, this is the first reported instance of a bonded GaN//GaAs wafer with a low electrical resistance.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Jun 5, 2019

Precursor flow rate manipulation for the controlled fabrication of twin-free GaAs nanowires on silicon substrates

Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metalorganic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700 ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

May 28, 2019

Surface and optical characteristics of polycrystalline GaN layer with different pores profile of porous GaAs/GaAs substrate

This work investigated the influence of pores profile of a porous GaAs or GaAs substrate on surface and optical characteristics of an over-deposited GaN layer. Different pores profile of the porous GaAs/GaAs substrate was introduced by varying the DMF concentration of 50%, 75% and 90%. The pores distribution is more uniform, while the pores size is bigger with higher DMF concentration. In contrast, the pores depth is less deep when the DMF concentration was higher than 75%. Next, the GaN layer was deposited onto the porous GaAs/GaAs substrate using an e-beam evaporator system, followed by thermal annealing in ammonia ambient. It was found that the porous GaAs/GaAs substrate, etched by the DMF concentration above 75% gave lower surface roughness to the polycrystalline GaN layer although the surface morphology showed no significant changes. XRD measurement showed on non-porous substrate favoured hexagonal growth in the polycrystalline GaN layer. Instead, the porous GaAs/GaAs substrate favoured the cubic growth, especially the porous GaAs/GaAs substrate etched by 75% DMF concentration. Moreover, the GaN layer on the porous GaAs/GaAs substrate etched by 75% DMF concentration showed the smallest FWHM of NBE peak emission, while exhibited a relaxation level closer to a reported stress-free bulk GaN, as compared to other samples. After all, the porous GaAs/GaAs substrate, etched by 75% DMF concentration has improved the surface and optical characteristics of the layer due to its better porosity.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

May 23, 2019

Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO2 mask

GaAs is grown by metal-organic vapor-phase epitaxy on a 55 nm round-hole patterned Si substrate with SiO2 as a mask. The threading dislocations, which are stacked on the lowest energy facet plane, move along the SiO2 walls, reducing the number of dislocations. The etching pit density of GaAs on the 55 nm round-hole patterned Si substrate is about 3.3 × 105 cm−2. Compared with the full width at half maximum measurement from x-ray diffraction and photoluminescence spectra of GaAs on a planar Si(001) substrate, those of GaAs on the 55 nm round-hole patterned Si substrate are reduced by 39.6 and 31.4%, respectively. The improvement in material quality is verified by transmission electron microscopy, field-emission scanning electron microscopy, Hall measurements, Raman spectroscopy, photoluminescence, and x-ray diffraction studies.



Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

May 16, 2019

Temperature dependent angular dispersions of surface acoustic waves on GaAs

We measure the phase velocities of surface acoustic waves (SAWs) propagating at different crystal orientations on (001)-cut GaAs substrates and their temperature dependance. We design and fabricate sets of interdigital transducers (IDTs) to induce 4 μm SAWs via the inverse piezoelectric (PZE) effect between the PZE [110] direction (set as θ = 0°) and the non-PZE [100] direction (θ = 45°) on GaAs. We also prepare ZnO film sputtered GaAs substrates in order to launch SAWs efficiently by IDTs even in the non-PZE direction. We quantify acoustic velocities between 1.4 and 300 K from the resonant frequencies in the S 11 parameter using a network analyzer. We observe parabolic velocity–temperature trends at all θ-values both on GaAs and ZnO/GaAs substrates. Below 200 K, in ZnO/GaAs substrates slower SAW modes appear around the [110] direction, which are unseen at RT.



Source:IOPscience


For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

May 9, 2019

In-situ atomic layer deposition of tri-methylaluminum and water on pristine single-crystal (In)GaAs surfaces: electronic and electric structures

The electronic structure of single-crystal (In)GaAs deposited with tri-methylaluminum (TMA) and water via atomic layer deposition (ALD) is presented with high-resolution synchrotron radiation core-level photoemission and capacitance-voltage (CV) characteristics. The interaction of the precursor atoms with (In)GaAs is confined at the topmost surface layer. The Ga-vacant site on the GaAs(111)A-2 × 2 surface is filled with Al, thereby effectively passivating the As dangling bonds. The As-As dimers on the GaAs(001)-2 × 4 surface are entirely passivated by one cycle of TMA and water. The presumed layerwise deposition fails to happen in GaAs(001)-4 × 6. In In0.20Ga0.80As(001)-2 × 4, the edge row As atoms are partially bonded with the Al, and one released methyl then bonds with the In. It is suggested that the unpassivated surface and subsurface atoms cause large frequency dispersions in CV characteristics under the gate bias. We also found that the (In)GaAs surface is immune to water in ALD. However, the momentary exposure of it to air (less than one minute) introduces significant signals of native oxides. This indicates the necessity of in situ works of high κ/(In)GaAs-related experiments in order to know the precise interfacial atomic bonding and thus know the electronic characteristics. The electric CV measurements of the ALD-Al2O3 on these (In)GaAs surfaces are correlated with their electronic properties.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Apr 30, 2019

Structural investigation of MOVPE-grown GaAs on Ge by x-ray techniques

The selection of appropriate characterization methodologies is vital for analyzing and comprehending the sources of defects and their influence on the properties of heteroepitaxially grown III–V layers. In this work, we investigate the structural properties of GaAs layers grown by metal-organic vapour phase epitaxy on Ge substrates—(1 0 0) with 6° offset towards 1 1 1〉—under various growth conditions. Synchrotron x-ray topography is employed to investigate the nature of extended linear defects formed in GaAs epilayers. Other x-ray techniques, such as reciprocal space mapping and triple axis ω-scans of (0 0 l)-reflections (l = 2, 4, 6), are used to quantify the degree of relaxation and presence of antiphase domains (APDs) in the GaAs crystals. The surface roughness is found to be closely related to the size of APDs formed at the GaAs/Ge heterointerface, as confirmed by x-ray diffraction (XRD), as well as atomic force microscopy and transmission electron microscopy.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Apr 24, 2019

Surface activated bonding of GaAs and SiC wafers at room temperature for improved heat dissipation in high-power semiconductor lasers

Thermal management of high-power semiconductor lasers is of great importance since the output power and beam quality are affected by the temperature rise of the gain region. Thermal simulations of a vertical-external-cavity surface-emitting laser by a finite-element method showed that the solder layer between the semiconductor thin film consisting of the gain region and a heat sink has a strong influence on the thermal resistance and direct bonding is preferred to achieve effective heat dissipation. To realize thin-film semiconductor lasers directly bonded on a high-thermal-conductivity substrate, surface-activated bonding using an argon fast atom beam was applied to the bonding of gallium arsenide wafer (GaAs) and silicon carbide (SiC) wafers. The GaAs/SiC structure was demonstrated in the wafer scale (2 in. in diameter) at room temperature. The cross-sectional transmission electron microscopy observations showed that void-free bonding interfaces were achieved.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Apr 18, 2019

Impact of LT-GaAs layers on crystalline properties of the epitaxial GaAs films grown by MBE on Si substrates

GaAs films with low-temperature GaAs (LT-GaAs) layers were grown by molecular beam epitaxy (MBE) method on vicinal (001) Si substrates oriented 6° off towards [110]. The grown structures were different with the thickness of LT-GaAs layers and its arrangement in the film. The processes of epitaxial layers nucleation and growth were controlled by reflection high energy electron diffraction (RHEED) method. Investigations of crystalline properties of the grown structures were carried out by the methods of X-ray diffraction (XRD) and transmission electron microscopy (TEM). The crystalline perfection of the GaAs films with LT-GaAs layers and the GaAs films without ones was comparable. It was found that in the LT- GaAs/Si layers the arsenic clusters are formed, as it occurs in the LT-GaAs/GaAs system without dislocation. It is shown that large clusters are formed mainly on the dislocations. However, the clusters have practically no effect on the density and the propagation path of threading dislocations. With increasing thickness of LT-GaAs layer the dislocations are partly bent along the LT-GaAs/GaAs interface due to the presence of stresses.


Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com