Aug 30, 2016

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Keywords: GaAs, Ge, Si, ELO, XRD,  insulator
Source: Iopscience

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Direct-bonded four-junction GaAs solar cells

Direct wafer bonding technology is able to integrate two smooth wafers and thus can be used in fabricating III–V multijunction solar cells with lattice mismatch. In order to monolithically interconnect between the GaInP/GaAs and InGaAsP/InGaAs subcells, the bonded GaAs/InP heterojunction must be a highly conductive ohmic junction or a tunnel junction. Three types of bonding interfaces were designed by tuning the conduction type and doping elements of GaAs and InP. The electrical properties of p-GaAs (Zn doped)/n-InP (Si doped), p-GaAs (C doped)/n-InP (Si doped) and n-GaAs (Si doped)/n-InP (Si doped) bonded heterojunctions were analyzed from the I–V characteristics. The wafer bonding process was investigated by improving the quality of the sample surface and optimizing the bonding parameters such as bonding temperature, bonding pressure, bonding time and so on. Finally, GaInP/GaAs/InGaAsP/InGaAs 4-junction solar cells have been prepared by a direct wafer bonding technique with the high efficiency of 34.14% at the AM0 condition

Keywords:III-V multijunction solar cells, GaInP/GaAs, InGaAsP/InGaAs subcells, GaAs/Inp heterojunction,

Source: Iopscience

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Jul 28, 2016

Strain-driven synthesis of 〈112〉 direction InAs nanowires in V-grooved trenches on Si using InP/GaAs buffer layers


We reported the 〈112〉 direction growth of InAs nanowires on patterned Si (001).
We proposed mechanism of 〈112〉 directions InAs nanowires and demonstrated.
We reported stacking-faults-free ZB InAs nanowires on Si (001).
InAs nanowires crystal quality was measured by TEM.


The catalyst-free metal organic vapor phase epitaxial growth of InAs nanowires on silicon (001) substrates is investigated by using selectively grown InP/GaAs buffer layers in V-grooved trenches. A strain-driven mechanism of self-aligned 〈112〉 direction InAs nanowires growing is proposed and demonstrated by the transmission electron microscopy measurement. The morphology of InAs nanowires is tapered in diameter and exhibits a hexagonal cross-section. The defect-free InAs nanowire shows a pure zinc blende crystal structure and an epitaxial relationship with InP buffer layer.


  • A1 Growth models
  • A3 Metal-organic chemical vapor deposition
  • B1 Nanomaterials
  • B1 Semiconducting III–V materials
        • SOURCE:Sciencedirector
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Jul 26, 2016

Native oxides formation and surface wettability of epitaxial III–V materials: The case of InP and GaAs


Wettability of binary, MOVPE grown, III–V materials (GaAs, InP, InAs) was investigated as a function of age and surface treatment.
XPS study was performed, to reveal the surface native oxides composition.
No trivial correlation between the oxide thickness/type and water drop contact angle was observed.


The time dependent transition from hydrophobic to hydrophilic states of the metalorganic vapour phase epitaxy (MOVPE) grown InP, GaAs and InAs is systematically documented by contact angle measurements. Natural oxides forming on the surfaces of air-exposed materials, as well as the results of some typical wet chemical process to remove those oxides, were studied by X-ray photoemission spectroscopy (XPS), revealing, surprisingly, a fundamental lack of strong correlations between the surface oxide composition and the reported systematic changes in hydrophobicity.


  • Hydrophobic surface
  • InP
  • GaAs
  • XPS
        • SOURCE:Sciencedirector
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Jul 19, 2016

InGaP/GaAs heterojunction photosensor powered by an on-chip GaAs solar cell for energy harvesting


In this study, an InGaP/GaAs heterojunction phototransistor (HPT) and a GaAs solar cell were monolithically integrated into an HPT epitaxial wafer, and the battery-free operation of the HPT was demonstrated for energy harvesting. Although the thickness and doping condition of the layers were optimized for the HPT performance, but not for the solar cell performance, the obtained short-circuit current was high enough to operate the InGaP/GaAs HPT in a two-terminal (2T) configuration. A collector photocurrent of 0.63 mA was obtained when the energy-harvesting InGaP/GaAs 2T-HPT was exposed to white light with a power density of 35 mW/cm2, and it linearly increased with the power density. For a potential application of the energy-harvesting InGaP/GaAs HPT as a photosensor in space, the device was irradiated with electrons of 1 MeV energy and 1015 cm−2 fluence. No significant degradation of the fabricated energy-harvesting 2T-HPT after the high-energy electron irradiation guarantees its battery-free operation in space.


A heterojunction phototransistor (HPT) is more attractive as a photosensor than a photodiode because of its high photoresponse even at low bias voltage and immunity from avalanche noise.13) In particular, the GaAs-based HPT with an AlGaAs emitter demonstrated a high performance. Recently, the InGaP emitter has replaced the AlGaAs emitter in the AlGaAs/GaAs HPT owing to its superior material properties.4) The photosensor may be widely used in space, where it needs to be operated without a battery. An HPT has a process compatibility with a heterojunction bipolar transistor (HBT) for the fabrication of monolithically integrated photoreceivers.5) The InGaP/GaAs HPT also has good compatibility with the GaAs heteroface solar cell for a battery-free operation. Solar cells made of III–V compound semiconductors have been developed and used in space owing to their high conversion efficiency, lower temperature coefficient, and superior radiation resistance.69) The significant potential of high-efficiency GaAs heteroface solar cells for space applications has been extensively investigated by many researchers.1017) Compared with Si, which has been widely used as a material of terrestrial solar cells, III–V compound semiconductors have a superior radiation resistance for the same electron energy and fluence. In particular, the InGaP solar cells demonstrated a radiation resistance superior to that of GaAs solar cells. Since the migration energy of radiation-induced defects and the activation energy of defect annealing in InGaP are lower than those in GaAs, InGaP has a higher radiation resistance than GaAs.18) In this study, radiation resistant InGaP was used as a window layer in a GaAs heteroface solar cell.
In space, high-energy electron or particle irradiation often induces a significant degradation of the performance of semiconductor devices. Since the battery-free operation of an InGaP/GaAs HPT monolithically integrated with a GaAs solar cell is also proposed for use in space in this paper, the effects of high-energy electron irradiation on the fabricated energy-harvesting HPTs were studied by 1 MeV electron irradiation.


  • GaAs/Si ; 
  •  AlGaAs/GaAs HPT 
    • SOURCE:iopscience
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Jun 20, 2016

Performance improvement mechanisms of pyramid-like via hole recessed GaAs-based solar cells grown on Si wafer


A recessed structure was used on the GaAs/Si solar cells to reduce the current path.
The associated series resistance was reduced by a recessed structure.
The carrier recombination loss was improved due to pyramid-like recessed structure.


In this study, epitaxial layers of GaAs-based solar cells were grown on Si substrates using a molecular beam epitaxial system. The pyramid-like via hole recessed electrode structure was fabricated on the back side of the Si substrate to improve the performance of the resulting solar cells. Since the current path was effectively reduced by the via hole recessed structure, the associated series resistance and the carrier recombination loss of the resulting GaAs/Si solar cells were decreased. Consequently, the conversion efficiency enhancement of 21.8% of the GaAs/Si solar cells with the via hole recessed structure was obtained due to the improvement in the short-circuit current density and the fill factor compared with the conventional GaAs/Si solar cells.


  • GaAs/Si solar cells
  • Low-temperature atomic layer epitaxy method
  • Molecular beam epitaxial system
  • Hole recessed structure                                                                                                              
    • SOURCE:Sciencedirector
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May 19, 2016

GaAs solar cell on Si substrate with good ohmic GaAs/Si interface by direct wafer bonding


We report wafer bonding (WB) techniques giving good ohmic interfaces of GaAs/Si.
WB with a low bonding temperature and short processing time was performed.
We demonstrated the GaAs solar cell on Si substrate by WB techniques.
Fabricated GaAs solar cell on Si exhibited a comparable performance with that on GaAs.
We proved the feasibility of stable WB technologies of GaAs/Si substrates.


In this work, we developed wafer bonding techniques to bond GaAs and Si wafers. Wafer bonding was carried out at room temperature without high temperature annealing processes. The bonded interface showed a low interface resistance of 8.8×10−3 Ω cm2. We also exploited the new bonding techniques to fabricate a GaAs solar cell on a Si substrate. The solar cell showed a high energy conversion efficiency (13.25%) even without an anti reflection coating. The performance of the fabricated GaAs/Si solar cell was comparable to that of a homogeneous GaAs solar cell grown on a GaAs substrate. *Corresponding author.


  • Wafer bonding
  • GaAs on Si
  • GaAs solar cell
  • GaAs/Si
      • SOURCE:Sciencedirector
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Mar 23, 2016

A review of molecular beam epitaxy of ferroelectric BaTiO3 films on Si, Ge and GaAs substrates and their applications

SrTiO3 epitaxial growth by molecular beam epitaxy (MBE) on silicon has opened up the route to the monolithic integration of various complex oxides on the complementary metal-oxide–semiconductor silicon platform. Among functional oxides, ferroelectric perovskite oxides offer promising perspectives to improve or add functionalities on-chip. We review the growth by MBE of the ferroelectric compound BaTiO3 on silicon (Si), germanium (Ge) and gallium arsenide (GaAs) and we discuss the film properties in terms of crystalline structure, microstructure and ferroelectricity. Finally, we review the last developments in two areas of interest for the applications of BaTiO3 films on silicon, namely integrated photonics, which benefits from the large Pockels effect of BaTiO3, and low power logic devices, which may benefit from the negative capacitance of the ferroelectric.


  • GaAs
  • germanium (Ge)
  • silicon(Si); 

    Feb 2, 2016

    Current transport mechanisms for heterojunctions of a-Se on various crystalline wafers (n-Si, p-Si and n-GaAs)

    Heterojunction diodes fabricated by thermal evaporation of p-type amorphous selenium (a-Se) on various crystalline wafers (n-Si, p-Si and n-GaAs) are analyzed by measuring their current–voltage (JV) characteristics. The measured JV characteristics for the investigated devices of configuration Au/a-Se/c-wafer/Al, exhibit a rectifying behavior and the bulk effect of the a-Se layer. For low forward voltage, the conduction mechanism is dominated by recombination of the carriers in the amorphous side of the space charge region. At higher voltage, the JV characteristics could be divided into two regions: an ohmic region and a space charge limited current region. The values of the activation energy obtained from the ohmic region are in agreement with those obtained from dc conductivity measurements in the same range of temperature. The reverse bias activation energy values at different temperatures are in agreement with those obtained from the temperature dependence of the forward saturation current, supporting the proposed recombination mechanism of conduction.


    • a-Se/c-Si
    • a-Se/c-GaAs
    • Heterojunctions
    • Amorphous/crystalline heterojunctions;
    • Transport mechanisms
    • Electron transport

    A novel growth strategy and characterization of fully relaxed un-tilted FCC GaAs on Si(1 0 0)


    Novel growth strategy of GaAs on Si(1 0 0) with AlAs/GaAs strain layer superlattice.
    Emphasis on understanding the inconclusive crystalline morphology at initial layers.
    Observed low TD in HRTEM and low RMS in AFM.
    Observed fourth order of superlattice peaks in ω–2θ scan in HRXRD.
    SAEDP shows fcc lattice and RSM study proves fully relaxed, un-tilted GaAs epilayer.


    A novel growth strategy for GaAs epilayer on Si(1 0 0) has been developed with AlAs/GaAs strained layer superlattice to achieve high crystalline quality for device applications. Emphasis has been given on understanding the inconclusive crystalline morphology of the initial layers by comprehensive material characterization. The influence of growth conditions have been studied by varying the growth temperatures, rates and V/III flux ratios. In-situ RHEED observations throughout the growth guided us to recognize the impact of individual growth parameters on the crystalline morphology. All the four stages of growth have been carried out by molecular beam epitaxy. The optimization of growth parameters at every stage initiates the formation of GaAs face centered cubic crystal from the very beginning. Material characterizations include AFM, HRTEM and HRXRD. The latter one, for the first time witnessed the intensity of superlattice satellite peaks in the fourth order. Low values of threading dislocation propagating to the top surface have been seen in HRTEM with absence of anti-phase boundaries (APB). Results for extended dislocations and surface roughness have been observed to be in the order of 106 cm−2 and 2 nm, respectively which is among the best reported values till date. Significant reduction of extended dislocations has been observed under strain fields in the superlattice. Notably, lower alloy mixing due to the optimized growth of AlAs/GaAs resulted in a suitable thermal behavioral platform as required for device applications. Fully relaxed, un-tilted, APB free, single domain and smooth GaAs epilayers have been achieved which paves the pathway to on-wafer integration of high performance III-Arsenide devices with Si logic circuits.


    Jan 4, 2016

    Periodic nanostructures fabricated on GaAs surface by UV pulsed laser interference


    Periodic nanostructures were fabricated on GaAs wafers by four-beam laser interference patterning which have potential applications in many fields.
    Significant different results were obtained on epi-ready and homo-epitaxial GaAs substrate surfaces.
    Two-pulse patterning was carried out on homo-epitaxial GaAs substrate, a noticeable morphology transformation induced by the second pulse was observed.
    Temperature distribution on sample surface as a function of time and position was calculated by solving the heat diffusion equations. The calculation agrees well with the experiment results.


    In this paper, periodic nanostructures were fabricated on GaAs wafers by four-beam UV pulsed laser interference patterning. Significant different results were observed on epi-ready and homo-epitaxial GaAs substrate surfaces, which suggests GaAs oxide layer has an important effect on pulsed laser irradiation process. In the case of two-pulse patterning, a noticeable morphology transformation induced by the second pulse was observed on homo-epitaxial GaAs substrate. Based on photo-thermal mode, temperature distribution on sample surface as a function of time and position was calculated by solving the heat diffusion equations.

    Graphical abstract

    Image for unlabelled figure