- Novel growth strategy of GaAs on Si(1 0 0) with AlAs/GaAs strain layer superlattice.
- Emphasis on understanding the inconclusive crystalline morphology at initial layers.
- Observed low TD in HRTEM and low RMS in AFM.
- Observed fourth order of superlattice peaks in ω–2θ scan in HRXRD.
- SAEDP shows fcc lattice and RSM study proves fully relaxed, un-tilted GaAs epilayer.
A novel growth strategy for GaAs epilayer on Si(1 0 0) has been developed with AlAs/GaAs strained layer superlattice to achieve high crystalline quality for device applications. Emphasis has been given on understanding the inconclusive crystalline morphology of the initial layers by comprehensive material characterization. The influence of growth conditions have been studied by varying the growth temperatures, rates and V/III flux ratios. In-situ RHEED observations throughout the growth guided us to recognize the impact of individual growth parameters on the crystalline morphology. All the four stages of growth have been carried out by molecular beam epitaxy. The optimization of growth parameters at every stage initiates the formation of GaAs face centered cubic crystal from the very beginning. Material characterizations include AFM, HRTEM and HRXRD. The latter one, for the first time witnessed the intensity of superlattice satellite peaks in the fourth order. Low values of threading dislocation propagating to the top surface have been seen in HRTEM with absence of anti-phase boundaries (APB). Results for extended dislocations and surface roughness have been observed to be in the order of 106 cm−2 and 2 nm, respectively which is among the best reported values till date. Significant reduction of extended dislocations has been observed under strain fields in the superlattice. Notably, lower alloy mixing due to the optimized growth of AlAs/GaAs resulted in a suitable thermal behavioral platform as required for device applications. Fully relaxed, un-tilted, APB free, single domain and smooth GaAs epilayers have been achieved which paves the pathway to on-wafer integration of high performance III-Arsenide devices with Si logic circuits.
- A3. MBE;
- GaAs on Si(1 0 0);
- AlAs/GaAs superlattice;
- SAED pattern
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