The quantitative analysis of the metallic contaminants both by chemical collection coupled to ICPMS and TXRF were implemented on GaAs and InP 100mm wafers. VPD-DC-ICPMS and LPD-ICPMS were developed respectively for GaAs and InP substrates. These methods present CE higher than 85% for usual metallic contaminants except for Cu & noble metals, and very sensitive detection thresholds are reached (108 to 1011 at/cm²). TXRF analysis conditions were optimized on both substrates. Na, Mg, Al, Ir and Ge on GaAs and K, Ca, Pd and Ag on InP are not analyzable due to substrate interferences. TXRF calibration was carried out from intentionally contaminated wafers in reference to ICPMS methods. Finally, TXRF enables to reach interesting detection limits (1010 to 1012at/cm² range) and is able to measure Cu and some noble metals.
Front end integration of III-V compound semiconductor devices with Si complimentary metal-oxide-semiconductor (CMOS) technology requires the development of commercially viable engineered substrates. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding and layer exfoliation. In this paper we report on the development of GaAs-on-insulator (GaAsOI) structures without the use of Smart Cut technology. Epitaxial GaAs/Ge/GaAs stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding. A room temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate was realized through room temperature, gas-phase lateral etching of the embedded Ge sacrificial layer by exposure to xenon difluoride (XeF2). This GaAsOI fabrication process is shown to be successful on a small scale, though implementation for the production of commercially-viable large area GaAsOI substrates at full wafer scale is currently limited by the long gas transport distance associated with a wafer-scale lateral etching process. In order to explore possibilities for overcoming this limitation we established a model that identifies the rate limiting processes and discuss potential approaches that will allow for the implementation of our gas phase lateral etching process for the fabrication of large diameter GaAsOI substrates.