Mar 31, 2014

CW and Q-switched mode-locking of a Nd:YVO/sub 4/ laser with a GaAs wafer

Summary from only given. We demonstrate the CW mode locking in a Nd:YVO/sub 4/ laser by using a single crystal GaAs wafer as the saturable absorber as well as the output coupler. We show that by simply changing the laser power density in the GaAs wafer either a pure CW mode locking or a Q-switched mode locking can be achieved.

Source:IEEE

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Mar 21, 2014

The Study of Femto-Second Laser Induced Damage Threshold on Semi-Insulating GaAs Wafer

We demonstrated an experiment of femtosecond-laser damage threshold on GaAs wafer, the damage threshold was measured from 50 to 400fs. The mechanism was discussed through injection power, pulse duration and ablation profile. The results showed that the damage threshold increased with the pulse duration, the relationship between diameter of ablation hole and laser power density was also analyzed. It was concluded that the main factor affecting the damage threshold was photon ionization and collision ionization.

Source: Chao Yang Li

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Mar 12, 2014

Design Of Experiment (DOE) For Thickness Reduction Of GaAs Wafer Using Lapping Process

This paper report a statistical method of performing wafer lapping experimental using design of experiment (DOE) technique in order to get best lapping time to reduced thickness of GaAs wafer. Lapping speed, lapping time, oscillator speed and weight was selected as four main factor determine the shortest time of thickness reduction. A complete 24 factorial of 4 factors (16 run) was design to determined the effect of selected factor. The lapping process was carried out using ULTRATEC Lapping& Polishing machine while the wafer thickness was characterized using Logitech non contact gauge. It was found that best lapping parameter was using lapping speed at 3 r.p.m, oscillator speed at 2 r.p.m and 3 weight block for duration of 240 sec. This parameter is able to reduce 156 mum of waferwithin 240 second without any crack problems and able to give good reference of reduction of GaAswafer thickness process period.

Source:IEEE

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Inductively coupled plasma reactive ion etching of GaAs wafer pieces with enhanced device yield

Inductively coupled plasma reactive ion etching (ICP-RIE) is used in the fabrication of GaAs slab-coupled optical waveguide (SCOW) laser and amplifier devices in order to prepare etched-ridge-waveguide surface features. The processing of GaAs wafer pieces (less than full wafers) requires mounting these samples on a ceramic or silicon carrier wafer by means of a thermally conductive mounting paste to improve thermal contact between the GaAs and carrier wafer. However, use of a mounting paste requires additional postetch handling of samples, including mechanical clean-up and multiple solvent cleaning steps. Insufficient paste removal can lead to unwanted surface contamination and film adhesion issues during subsequent sample processing. Massachusetts Institute of Technology Lincoln Laboratory has developed an ICP-RIE process for GaAs wafer pieces that eliminates the use of mounting paste. This process features time-limited thermal management during etching, which is essential to maintain predictable etch rates along with suitable etched surfaces and satisfactory sidewall quality. Utilizing this simplified etch process for SCOW fabrication has resulted in greatly reduced film adhesion failures and a dramatic improvement in device yield.

Source:IEEE

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Mar 5, 2014

Surface defects in GaAs wafer processes

The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 μm in TTV and the warp to less than 5 μm. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

Source: Journal of Crystal Growth

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Fabrication of GaAs laser diodes on Si using low-temperature bonding of MBE-grown GaAs wafers with Si wafers

We present a study of the properties of III–V structures integrated on Si by low-temperature GaAs–Si wafer bonding, using an intermediate spin-on-glass layer. Transmission electron microscopy revealed the good quality of the bonding and the absence of micro-cracks or dislocations in the semiconductor material. Photoluminescence measurements on GaAs/AlGaAs multiple quantum well structures bonded on Si confirmed that the structural integrity of the quantum wells was preserved during the wafer bonding and thinning process. Photoreflectance measurements at temperatures in the range of 80–300 K showed that the bonded GaAs layers were practically stress free at room temperature, while a tensile stress appeared at lower temperature, due to the different thermal expansion coefficients of GaAs and Si. Laser devices with etched mirrors were fabricated on silicon and exhibited similar performances with reference devices fabricated on a GaAs substrate.

Source: Journal of Crystal Growth

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